Tiny Block Cipher

Description:

This project implements a compact, sequential lightweight block cipher core designed for TinyTapeout-compatible hardware deployment. The cipher uses a PRESENT-inspired architecture with a 64-bit block size, 80-bit key, and 16 encryption rounds, reusing datapath hardware across cycles to minimize area. Its Verilog design includes AddRoundKey logic, a 4-bit S-box substitution layer, a fixed bit-permutation layer, an 80-bit key schedule, and an FSM-based controller that manages loading, encryption, and completion. The project also defines a byte-oriented TinyTapeout I/O protocol and includes simulation support through cocotb and Icarus Verilog testbenches, demonstrating skills in digital design, cryptographic hardware, RTL implementation, and verification.