FPGA Sorting Hardware Accelerator

FPGA Sorting Hardware Accelerator

Description:

Developed a high-performance sorting accelerator on an iCE40 FPGA, featuring a UART interface for real-time communication with a host PC. The system receives unsorted 8-bit integer datasets, processes them on-chip using an optimized radix sort algorithm based on base-10 digit extraction (modulo and division), and returns the sorted results to the PC. The design leverages a multi-state finite state machine (FSM) to efficiently manage the sequential steps of bucketing, reordering, and transmitting data, ensuring low-latency, hardware-accelerated sorting suitable for embedded applications.